1. Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to a technique for incorporating additional addressable registers into an existing microprocessor instruction set architecture.
2. Description of the Related Art
Since microprocessors were fielded in the early 1970's, their use has grown exponentially. Originally applied in the scientific and technical fields, microprocessor use has moved over time from those specialty fields into commercial consumer fields that include products such as desktop and laptop computers, video game controllers, and many other common household and business devices.
Along with this explosive growth in use, the art has experienced a corresponding technology pull that is characterized by an escalating demand for increased speed, expanded addressing capabilities, faster memory accesses, larger operand size, more types of general purpose operations (e.g., floating point, single-instruction multiple data (SIMD), conditional moves, etc.), and added special purpose operations (e.g., digital signal processing functions and other multi-media operations). This technology pull has resulted in an incredible number of advances in the art which have been incorporated in microprocessor designs such as extensive pipelining, super-scalar architectures, cache structures, out-of-order processing, burst access mechanisms, branch predication, and speculative execution. Quite frankly, a present day microprocessor is an amazingly complex and capable machine in comparison to its 30-year-old predecessors.
But unlike many other products, there is another very important factor that has constrained, and continues to constrain, the evolution of microprocessor architecture. This factor—legacy compatibility—furthermore accounts for much of the complexity that is present in a modern microprocessor. For market-driven reasons, many producers have opted to retain all of the capabilities that are required to insure compatibility with older, so-called legacy application programs as new designs are provided which incorporate new architectural features.
Nowhere has this legacy compatibility burden been more noticeable than can be seen in the development history of x86-compatible microprocessors. It is well known that a present day virtual-mode, 32-/16-bit x86 microprocessor is still capable of executing 8-bit, real-mode, application programs which were produced during the 1980's. And those skilled in the art will also acknowledge that a significant amount of corresponding architectural “baggage” is carried along in the x86 architecture for the sole purpose of supporting compatibility with legacy applications and operating modes. Yet while in the past developers have been able to incorporate newly developed architectural features into existing instruction set architectures, the means whereby use of these features is enabled—programmable instructions—are becoming scarce. More specifically, there are no more “spare” instructions in certain instruction sets of interest that provide designers with a means to incorporate newer features into an existing architecture.
In the x86 instruction set architecture for example, there are no undefined 1-byte opcode states that have not already been used. All 256 opcode states in the primary 1-byte x86 opcode map are taken up with existing instructions. As a result, x86 microprocessor designers must presently make a choice between providing new features and abandoning legacy compatibility. If new programmable features are to be provided, then they must be assigned to opcode states in order for programmers to exercise those features. And if spare opcode states do not remain in an existing instruction set architecture, then some of the existing opcode states must be redefined to provide for the new features. Thus, legacy compatibility is sacrificed in order to provide for new feature growth.
On area of growth that continues to plague microprocessor designers involves the number and use of addressable registers within a microprocessor. Early microprocessor designs provided for one or two general purpose 8-bit registers. Then, as computations within application programs became more complex, both the number and size of the general purpose registers grew. The present state of the art in microprocessors that are employed in desktop/laptop computing applications provides for less than 10 general purpose 32-bit registers. But even at present, there are application programming areas that are disadvantageously impacted because present day microprocessors do not provide more addressable registers for general purpose operations.
Therefore, what is needed is an apparatus and method that incorporate additional general purpose registers into an existing microprocessor instruction set architecture that has a completely full opcode set, and where incorporation of the technique additionally allows a conforming microprocessor to retain the capability to execute legacy application programs.